1. Field of the Invention
The present invention relates generally to comparator circuits and in particular to high speed integrated circuit comparator circuits.
2. Description of Related Art
Comparator circuits are frequently employed in Analog-To-Digital (ADC) circuits and other types of data conversion devices. FIG. 1 is a schematic diagram of a conventional auto-zeroing capacitively coupled comparator circuit, generally designated by the numeral 10, which can be implemented in integrated circuit form and is frequently used in ADC circuits. The comparator circuit 10 includes a first input Vin and a second input Vref, both of which are positive voltages for single supply operation. Typically, Vin is an analog input which is to be compared with a fixed reference voltage, such as Vref. Inputs Vin and Vref are buffered by non-inverting amplifiers 12 and 14, respectively.
Comparator circuit 10 includes two compare amplifiers 16 and 18 which are connected together in a cross-coupled configuration. The output of amplifier 16 is connected to the input of amplifier 18 by way of a first feedback capacitor 20 and the output of amplifier 18 is connected to the input of amplifier 16 by way of a second feedback capacitor 22 equal in value to capacitor 20. Amplifiers 16 and 18 receive inputs through a pair of equal value input capacitors 24 and 26, respectively. The input capacitors 24 and 26 are typically two times larger in value than the feedback capacitors 20 and 22.
The outputs of the cross-coupled amplifiers 16 and 18 are connected to an output latch circuit which includes input NMOS transistors 28 and 30 and pull-up PMOS transistors 32 and 34. The common drain connection of transistors 28 and 32 is connected to the gate of transistor 34 and the common drain connection of transistors 30 and 34 being connected to the gate of transistor 32. The output latch includes first and second output buffers 40 and 42 having respective inputs connected to the common drain connection of transistors 28 and 32 and the common drain connection of transistors 30 and 34, respectively. The outputs of buffers 40 and 42 form the outputs Vout.sup.- and Vout.sup.+, respectively, of the comparator circuit 10.
The operation of comparator circuit 14 is controlled by a pair of non-overlapping clock signals S (sample) and H (hold). FIGS. 2A and 2B are timing diagrams which represent signals S and H, respectively. At time T.sub.0, the hold signal H is low and sample signal S goes high thereby indicting that the comparator circuit is in the sample phase of operation. (Note that the timing diagram is not to scale with respect to either the magnitude axis or the time axis.) Under these conditions, transistor switch 44 is conductive so that input Vin will be applied to one terminal of input capacitor 24 by way of unity gain amplifier 12. Similarly, transistor switch 46 is conductive so that input Vref will be applied to one terminal of input capacitor 26 by way of unity gain amplifier 14. The low hold signal H will cause transistor switch 48 to be off.
The inverted signal H, which is high at this time (T.sub.0), is applied to transistor switches 50 and 52 so that both switches will be conductive. Switch 50 will connect the input and output of compare amplifier 16 directly together. This will cause the input and output to be at the threshold voltage or virtual ground of amplifier 16, that typically being on the order of a fraction of a volt. Note that the compare amplifiers 16 and 18 need to be inverting for this threshold voltage or virtual ground to be established. Switch 52 performs a similar function in connection with compare amplifier 18. Under these conditions, input capacitor 24 will have a voltage drop equal to the difference between the input threshold voltage of amplifier 16 and input Vin. Similarly, input capacitor 26 will have a voltage drop equal to the difference between the input threshold voltage of amplifier 18 and input Vref assuming that the buffer amplifiers are ideal and perfectly reproduce Vin and Vref. In the present example, and as can be seen in FIGS. 2D and 2E (not to scale), input Vin is +550 mv during the first sample phase depicted in the timing diagram and is thus slightly larger than the fixed reference voltage Vref of +500 mv.
During the sample phase, the output latch is placed in a disable state by control transistors 36 and 38, both of which are larger than pull-down transistors 28 and 30. Since inverted signal S is low at this time, the PMOS transistors 36 and 38 will both be conductive thereby forcing the inputs to the buffer circuits to a high state so that both outputs Vout+ and Vout- will be low (inactive) as can be seen in FIGS. 2G and 2H. This is true regardless of the state of the smaller pull-down transistors 28 and 30 which, at this point, have gate voltages equal to the respective threshold voltages of amplifiers 16 and 18.
At time T.sub.1, signal S goes low and, at a small time later, T.sub.2, signal H goes high thereby causing the comparator circuit 14 to enter the hold phase. The low signal S will first turn off switches 44 and 46 thereby isolating the input capacitors 24 and 26 from the outputs of amplifiers 12 and 14. Further, control transistors 36 and 38 will turn off since signal S is high so that the output latch will be operative and will tend to be in a neutral state so that there will be little preference for the output latch to switch to one state over another state. Thus, the output latch is in condition to be set to either output state, Vout.sup.+ active or Vout.sup.- active, in response to the relatively weak outputs of the compare amplifiers 16 and 18. The subsequent increase in signal H at time T.sub.2 will result in the input terminals of input capacitors 24 and 26 being connected together and the switches 50 and 52 being opened thereby removing the connection between the input and output of compare amplifiers 16 and 18.
Connecting the input terminals of the input capacitors 24 and 26 together will cause the two capacitors to be connected in series between the inputs of the compare amplifiers 16 and 18. The total voltage drop across the series connection of the two capacitors will be substantially equal in magnitude to the difference in Vin and Vref. This assumes that the input capacitors 24 and 26 are significantly larger than the capacitances due to wiring, amplifier inputs and other parasitics. The polarity of the drop across the capacitors will be such that the input of amplifier 16 will be reduced below the threshold voltage of amplifier 16 by an amount equal to approximately one-half of the voltage difference and the input of amplifier 18 will be increased above the threshold voltage of amplifier 18 by an amount equal to approximately one-half the voltage difference. The drop in input voltage to amplifier 16 will be amplified and inverted by the amplifier. The rise in output voltage of amplifier 16 is capacitively coupled to the input of amplifier 18 thereby reinforcing the increase in voltage applied to the input of amplifier 18. The resultant drop in the output of amplifier 18 is capacitively coupled to the input of amplifier 16 thereby reinforcing the drop in voltage applied to the amplifier input. This regenerative action causes the compare amplifiers 16 and 18 to exhibit a large amount of closed loop gain, much greater than the open loop gain of the individual amplifiers. It can be further appreciated that any difference between input threshold voltage of the two amplifiers 16 and 18 is compensated for automatically.
At this point in time, T.sub.3, the output of compare amplifier 18 will begin rapidly decreasing in value and the output of compare amplifier 16 will begin increasing rapidly. Eventually, the regenerative action provided by the cross-coupled feedback capacitors 20 and 22 will cause either transistor 28 to start to turn on or transistor 30 to start to turn off or a combination of both. The resultant drop in the drain voltage of transistor 28 will cause transistor 34 to begin to turn on and the resultant increase in drain voltage of transistor 30 will cause transistor 32 to begin to turn off. Eventually, this regenerative action will cause the output latch to rapidly switch to a state so that output Vout.sup.+ is active (V.sub.CC) and Vout.sup.- is inactive (V.sub.SS) at time T.sub.3. Thus, it can be seen that the output latch provides a comparison function and a level shifting function by detecting the relative magnitudes of the outputs of compare amplifiers 16 and 18 and by providing outputs Vout.sup.+ and Vout.sup.- at standard CMOS levels. The input comparator stage, which includes compare amplifiers 16 and 18 and associated circuitry, can be considered to be in a measure state during the hold phase just prior to time T.sub.3 and to be in one of two possible output states after T.sub.3. One output state will cause only Vout.sup.+ to be active and the other output state will cause only Vout.sup.+ to be active.
In a second exemplary compare operation, starting at time T.sub.4, Vin will have dropped from 550 mv to 450 mv so that Vin is now 100 mv less than Vref. The operation of the comparator circuit 14 is similar to that previously described except that Vout.sup.+ will go active (high) at time T.sub.6. Vout.sup.+ will remain inactive.
The above-described comparator circuit 14 provides satisfactory operation at normal operating speeds. However, as the speed requirements of ADCs and other similar circuits using comparators increases, comparator circuit 14 has been found to be inadequate.
There is a need for comparator circuits having improved high frequency operating characteristics. The comparator circuit in accordance with the present invention provides such improved operating characteristics and can be easily implemented in integrated circuit form. These and other advantages of the present invention will become apparent to those skilled in the art upon a reading of the following Detailed Description of the Invention together with the drawings.